This invention relates to integrated semiconductor memory cells, in each of which a charge pump is formed of a MOS capacitor acting as a load element for the flip-flop circuit of the memory cell.
There is set forth in a publication issued by the "IEEE International Solid State Circuits Conference" (Feb. 16, 1972, pages 16, 17) a static RAM including memory cells each utilizing a charge pump constituted by a MOS capacitor instead of a MOS transistor to act as a load element for the flip-flop circuit of the memory cell. FIG. 1 shows an equivalent circuit of this static memory cell. The memory cell of FIG. 1 is provided with a flip-flop circuit including a pair of driver MOS transistors Q1 and Q2 whose sources are connected together; a load MOS capacitor C1, one of whose electrodes is connected to the drain of the driver MOS transistor Q1 and the gate of the driver MOS transistor Q2; and a load MOS capacitor C2, one of whose electrodes is connected to the drain of the driver MOS transistor Q2 and the gate of the driver MOS transistor Q1. A clock pulse having a prescribed frequency is supplied to the other electrodes of the load MOS capacitors C1 and C2 to cause them to act as charge pumps. The output terminals Q and Q of the flip-flop circuit are connected to digit lines D and D through the coresponding address-selection MOS transistors Q3 and Q4. The gates of these transistors Q3 and Q4 are jointly connected to a word line W.
The disclosed memory cell in which a charge pump is used as a load element for a flip-flop circuit has a noticeable merit of reducing an area occupied by the memory cell. Various attempts have been proposed to decrease the area of the memory cell.